(1) Field of the Invention
This invention relates generally to memory products and relates more specifically to reference cell architectures for memories that need to activate small array blocks.
(2) Description of the Prior Art
In read operation of memory chips, a sense amplifier compares a stored signal with a reference signal. This concept applies to all of the semiconductor memories except those that store true and complement data in a cell such as SRAM's and twin-cell memories. The reference signal is created to provide the middle voltage or current level between stored 1 and 0 of the memory data. Although its storage mechanism exploits magnetization, a sensing operation of Magnetic Random Access Memories (MRAM) using Magnetic Tunnel Junction (MTJ) also compares the current of a stored cell with that of the reference, because magnetization direction of the free layer, either parallel or anti-parallel to the fixed layer, causes a difference in electrical resistance across MTJ, and this can be detected as the difference in current.
FIGS. 1a+b prior art show examples how the reference signal is generated in conventional MRAMs. FIG. 1a prior art shows a conventional MRAM Array structure in regard of a reference bit line. FIG. 1b prior art shows a conventional MRAM Array structure in regard of a reference bit word line.
It is assumed that the memory in the example of FIGS. 1a+b prior art has 16 data I/Os (DQs). The first example shown in FIG. 1a prior art uses a reference bit line (RefBL) 1. Typically, one RefBL is allocated in every 16 or 32 bit lines 2 for each data I/O. It provides the middle current of stored 1 and 0 levels by using either analog circuit design technique or actual cells. There are two types of word lines. For a write operation, the write word line (WWL) by a metal layer carries word line current to generate magnetic filed underneath MTJ in addition to bit line current. A read word line (RWL) is connected to all of 256-512 gates of nMOS cell transistors. Generally, a RWL consists of two layers; the first one is poly-Si layer, which is gate of nMOS cell transistor. The second is one is a metal layer, and this straps poly-Si layer at every 16-32 cells to reduce the resistance of RWL. In a typical MRAM array block, there are 256-1024 WWLs and RWLs. During read, a bit line multiplexing block, Mux, selects one of 16-32 bit lines as the input to a sense amplifier according to an accessed address. The sense amplifier compares the reference current on RefBL with that of the selected bit line.
For a folded bit line structure, a pair of reference word lines (RefWLs) can be used. FIG. 1b prior art shows this scheme as a second example of the conventional MRAM reference In FIG. 1a prior art, a cell transistor gate 4 is placed on every crossing point of bit line 2 and RWL as shown by dots 4. However, in the folded bit line scheme of FIG. 1b prior art, RWL has cell transistor gate 4 on its every second crossing point of bit line 2. Thus, when a bit line is accessed by turning on the cell transistor, its adjacent bit line is not accessed. Therefore, if a Reference Word Line (RefWL) is arranged so that its activation turns on the cell transistor on this un-accessed bit line, this adjacent bit line can be used as the reference bit line. For simplicity, two RefWLs are shown in FIG. 1b prior art, but actually each RefWL consists of two lines, one is connected to a reference cell with stored data 1, and the other to a stored data 0. The data from these two cells are connected to the bit line to supply a sum of stored 1 and 0 current. The current is mirrored to a half to become the reference current for the sense amplifier. If the top RWL of FIG. 1b prior art is selected the cell current on the left edge bit line, the bottom RefWL is turned on to conduct the reference current on the adjacent bit line on right. The multiplexer Mux selects these two bit lines, and the sense amplifier compares the currents on them during the read access.
Both examples shown in FIGS. 1a+b prior art are applicable to the conventional MRAM array architecture that activates one cell among 16-32 cells on the same RWL/WWL for read and write operations. Thus, during writes, only one cell is selected among many surrounding cells, and all unselected cells are subject to half select write disturb either by bit or word write current. It is very difficult to optimize current levels in terms of robustness to write disturb on bit and word directions. This is the well-known major issue of MRAMs.
For this fundamental issue, array architecture to write all of the cells on the same WWL may be regarded as a promising way. Because of no word line disturb, the MTJ shape and bit/word write currents could be optimized by considering bit direction disturb only. FIGS. 7a+b prior art show an example of this architecture. As shown FIG. 7a prior art an array block is segmented by the short WWL with a tail transistor. There is a switch on the source side of Write Word Line. Depending on the accessed address, the chip selects one of the segments choosing the source side switch. A write select line is connected to the gates of all tail transistors. Thus, activating one Write Select Line (WSL) enables the word line write current of 16 or 32 cells in the selected segmented small array only. These 16 or 32 bit lines in each segment provide 16 or 32 I/O data. FIG. 7b prior art illustrates a physical cross section along the bit line. At the very bottom, a poly-Si line, which is connected to gates of 16-32 cell transistors, runs perpendicular to the bit line. This poly-Si line is strapped to a higher-level metal layer at both ends of the segment. Above this strapping metal layer, another higher-level metal runs in parallel as WSL, which is connected to the gate of the tail transistor at one end of the segment. Further above it and just below MTJ, WWL runs in the same direction. At the very top, the bit line runs perpendicularly to all of underneath lines, WWL, WSL, RWL, and poly-Si wire.
In such an architecture, there is no word line write disturb, but since all of the 16 or 32 cells in this one segment need to be read at a time, the conventional reference current circuits shown in FIGS. 1a+b prior art cannot be used. An open bit line scheme is well-known array architecture used in DRAM, and it can be used for the segmented MRAM array. In this open bit-line scheme a block of sense amplifiers is located with multiplexing switches between two identical, mirrored arrays. In each array, two sets of RefWLs are placed at the edge (closer side to sense amplifier) of the array. RefWL consists of the same components as actual memory, WWL, WSL, RWL, and poly-Si line. Each of two RefWLs stores data 1 and 0 respectively to flow the summed current on the bit line, which is mirrored to a half to give the middle level of stored 1 and 0 to become the reference current in the sense amplifier. For a read, when a RWL on the top array is selected, RWLs of two RefWLs on the bottom array is selected. The sense amplifier compares read current from the top array and the reference current from bottom. This open bit line scheme fits the segmented array architecture quite well, but the open bit line scheme has less robustness to noise compared to a folded bit line scheme. Because RWL and RefRWL are placed on different array blocks, noise induced in here is not common-mode generally.
It is a challenge for engineers to realize reference current circuits for reliable sensing operations in segmented MRAM and other memory architectures.
There are known patents or patent publications dealing with sensing operations of MRAM arrays:
U. S. Patent Publication (US 2007/0247939 to Nahas et al.) proposes a magnetoresistive random access memory (MRAM) avoiding difficulties with write disturb by electrically isolating the portion of the array with data from the portion with reference signals while providing fast read speeds by simultaneously enabling the word line having the reference cells and the selected word line. For high speed accessing it is difficult to completely stabilize a precharge prior to beginning the next access. Accordingly, it is desirable for the reference cell and the selected cell to have the same response characteristics because no voltages are truly stationary during high speed accessing. This is achieved by simultaneous accessing and by having matched impedances. Thus, the voltage separation between the reference cell and the selected cell can be maintained even when both are moving even if they are moving in the same direction.
U.S. patent (U.S. Pat. No. 7,453,719 to Sakimura et al.) discloses an MRAM having a plurality of bit lines, a reference bit line, a plurality of memory cells and reference cells and a read section. The memory cells are provided along the bit lines and the reference cells along the reference bit line. The memory cell and reference cell have a tunneling magnetic resistance and a reference tunneling magnetic resistance, each of which has a spontaneous magnetization whose direction is reversed in accordance with data stored therein. The read section has a first resistance section which contains a ninth terminal connected with a bit line and a tenth terminal connected with the first power supply, a second resistance section which contains an eleventh terminal connected with the reference bit line and a twelfth terminal connected with the first power supply, and a comparing section which compares a sense voltage on the ninth terminal and a reference voltage of the eleventh terminal.
U.S. patent (U.S. Pat. No. 6,807,089 to Gogl et al.) discloses a method for operating an MRAM semiconductor memory configuration for the purpose of reading an item of stored information wherein reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.
Furthermore the following publications are dealing with reference lines of MRAM arrays:
M. Durlam et al., “A 1-Mb MRAM Based on 1T1MTJ Bit Cell Integrated With Copper Interconnects”, IEEE Journal of Solid-State Circuits, vol. 38 no. 5, pp. 769-773, May 2003,
J. DeBrosse et al., “A High-Speed 128 Kb MRAM Core for Future Universal Memory Applications”, IEEE Journal of Solid-State Circuits, vol. 39 no. 4, pp. 678-683, April 2004,
N. Sakimura et al., “A 250 MHz 1-Mb Embedded MRAM Macro Using 2T1MTJ Cell with Bit Line Separation and Half-Pitch Shift Architecture”, Proceedings of 2007 IEEE Asian Solid-State Circuits Conference, pp. 216-219, November 2007, and
T. Tsujii et al., “A 1.2V IMbit Embedded MFUM Core with Folded Bit-Line Array Architecture”, IEEE Symposium VLSI Circuits Digest of Technical Papers, pp. 450-453 June 2004.